Create Your RTL Simulations With KiCAD

[Bob Alexander] is in the process of designing a homebrew discrete TTL CPU, and wanted a way to enter schematics for digital simulations via a Verilog RTL flow. Since KiCAD is pretty good at handling hierarchical schematics, why not use that? [Bob] created a KiCAD plugin, KiCadVerilog allowing one to instantiate and wire up the circuits under consideration, and then throw the resulting Verilog file at your logic simulator of choice.

KiCadVerilog doesn’t do all the hard work though, as it only provides the structure and the wiring of the circuit. The actual guts of each TTL instance needs to be provided, and a reference to it is manually added to the schematic object fields. That’s a one-time deal, as you can re-use the component library once generated. Since TTL logic has been around for a little while, locating a suitable Verilog library for this is easy. Here’s ice-chips-verilog by [TimRudy] on GitHub for starters. It’s intended as a collection for Icestudio (which is also worth a look). Still, the Verilog code for many TTL series devices is presented ready for the taking, complete with individual test benches in case you need them.

Check out the project GitHub page for the module source code, and some more documentation about the design process.

We’ve seen many RTL hacks over the years, here’s an interesting way to generate a PCB layout with discrete logic, direct from the RTL.

Luis Robinson

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